Many semiconductor memory devices typically include memory cells of one type. Such semiconductor memory devices may include one or more arrays of one type of memory cell (e.g., dynamic random access memory (DRAM) cells). However, semiconductor memory devices may also have two or more memory sections, where each of which may contain a different memory type.
To improve quality and reliability, semiconductor memory devices may be subject to a "burn-in" test. A burn-in test can be a type of screening that operates a device at a high temperature, typically about 125.degree. C. Such a higher temperature can accelerate latent defects, thus detecting devices that may initially operate normally, but subsequently fail over time.
Conventionally a burn-in test can follow the normal operation of a semiconductor device. Consequently, in a semiconductor memory device that includes two or more memory sections, only one memory section is tested at a time. Thus, a burn-in test for such devices can switch between memory sections, stressing only one individual memory section at a time. As a result, the more memory sections a semiconductor device includes, the longer a burn-in test may take. Longer burn-in tests can slow manufacturing throughput and/or increase testing costs.
To better understand the present invention, a conventional semiconductor storage device having two memory sections, and a corresponding normal and burn-in test mode will now be described. Referring now to FIG. 5, a conventional semiconductor storage device is shown that includes two memory sections, a random access memory (RAM) section 10 and a read-only-memory section 20. Herein, a RAM section 10 will be referred to as a first memory section and a ROM section 20 will be referred to as a second memory section. The first and second memory sections (10 and 20) may include respective memory cell arrays, and peripheral circuits that may receive and decode an applied address to access memory cells within each memory section (10 and 20).
FIG. 5 is shown to particularly include a first memory section (RAM) 10 that includes a first memory cell array 11, a first address buffer 12, a first address decoder 13, a first X decoder 14, a first Y selector 15, and a first sense amplifier 16. Similarly, a second memory section (ROM) 20 may include a second memory cell array 21, a second address buffer 22, a second address decoder 23, a second X decoder 24, a second Y selector 25, and a second sense amplifier 26.
An address, represented as AD0, AD1 . . . , can be supplied to first and second address buffers (12 and 22). First and second address buffers 12 and 22 can be connected to first and second address decoders 13 and 23, respectively. First address decoder 13 may be connected to first X decoder 14 and first Y selector 15. Second address decoder 23 may be connected to second X decoder 24 and second Y selector 25. The first X decoder 14 and Y selector 15 may be connected to first memory cell array 11, while second X decoder 24 and Y selector 25 may be connected to second memory cell array 21. A first memory cell array 11 may be connected to first sense amplifier 16 and second memory cell array 21 may be connected to second sense amplifier 26.
The conventional semiconductor storage device of FIG. 5 may also include a write enable (W/E) circuit 30, a first selection circuit 41' and a second selection circuit 42'. A W/E circuit 30 may place a first memory section 10 in a write mode. In FIG. 5, a W/E circuit 30 may be connected to a first sense amplifier 16 and a common input/output (I/O) buffer circuit 50.
A first selection circuit 41' may be connected to a memory section selection pin (pin0') and can activate or deactivate a first memory section 10, while a second selection circuit 42' may be connected to a second selection pin (pin1') and can activate or deactivate a second memory section 20.
In operation, a first selection circuit 41' may provide a first chip selection signal CE10 to a first address buffer 12 by way of a first inverter 46. A second selection circuit 42' may provide a second chip selection signal CE20 by way of a second inverter 47. First and second selection circuits (41' and 42') can also be connected to common I/O buffer circuit 50
A common I/O buffer circuit 50 can serve to reduce the number of external I/O pins necessary for outputting and/or inputting data to the first or second memory sections (10 and 20).
As noted above, a typical conventional burn-in test for a semiconductor storage device can be conducted while the semiconductor storage device is operating in a normal manner. Thus, for a semiconductor storage device such as that shown in FIG. 5, one of the memory sections (10 or 20) can be selected by providing a particular logic value (e.g., a low logic value) as an input to a first selection circuit 41' or a second selection circuit 42'.
By way of example, assume that a low logic value is supplied as an input to first selection circuit 41' at memory section selection pin0'. A low pin0' value can result in the first chip section selection CE10 being active (e.g., high). An active CE10 signal can select the first memory section 10.
Next, assume that a low logic value is supplied to as an input to the second selection circuit at memory selection pin1'. In this case, a low pin1' value can result in the second chip section selection CE20 being active (e.g., high). An active CE20 signal can select the second memory section 20.
If both first and second selection pins (pin0' and pin1') receive inactive levels (e.g., high), both first and second memory sections (10 and 20) can be disabled.
However, if both first and second selection pins (pin0' and pin1') receive active levels, both first and second memory sections (10 and 20) can be enabled. Such a state is not desirable in a normal mode of operation as first and second memory sections (10 and 20) can share a common I/O buffer circuit 50, and multiple data sets could arrive at the same time providing invalid results. For these reasons, conventional semiconductor storage devices that follow normal modes of operation during a burn-in test have activated only a first or second memory section (10 and 20) in such a burn-in test.
As noted above, in the normal operation of a conventional semiconductor storage device, first and second memory sections are not activated simultaneously. Thus, because a burn-in test can follow a normal operating procedure, burn-in tests can be conducted as shown in FIG. 6A.
FIG. 6A shows access to memory cells during a burn-in test in a conventional semiconductor storage device. As shown in FIG. 6A, initially a low value is applied to memory section selection pin0' and a high value is applied to memory section selection pin1' to access a first memory section 10. Subsequently, a high value is applied to memory section selection pin0' and a low value is applied to memory section selection pin1' to access a second memory section 20. Such an arrangement can increase test times, as each memory section (10 and 20) is activated one after the other.
Various other conventional approaches related to the present invention are known. Japanese Patent Laid-Open No. 6-84396 (hereinafter referred to as "prior art 1"), describes a semiconductor storage device designed to reduce a dynamic bias test time (BT). In prior art 1, a semiconductor storage device can include multiple memory sections. When a test signal is inactive, one section selection signal can be activated according to an address signal. When a test signal is active, all section selection signals can be activated, allowing all sections to operate in parallel.
Japanese Patent Laid-Open No. 4-298900 (hereinafter referred to as prior art 2) describes a semiconductor memory apparatus designed to simplify the circuit configuration of an operation stress acceleration testing (BT) apparatus. The approach is believed to increase the number of BT tests that may be conducted simultaneously, reduce the cost of a BT testing apparatus, and improve the reliability and range of applications for such an apparatus.
In prior art 2, a semiconductor memory apparatus can include a voltage detection circuit that can generate a voltage monitoring signal. The voltage monitoring signal may be active when a voltage higher than a predetermined reference voltage is applied to a particular terminal. In addition, a clock generator may generate a clock signal when the voltage monitoring signal is active. A test signal generator may then generate a test signal, each according to the clock signal. A switching circuit is provided that supplies each test signal to an internal circuit when the voltage monitoring signal is active.
Japanese Patent Laid-Open No. 6-60697 (hereinafter referred to as prior art 3) describes a semiconductor memory apparatus designed to reduce burn-in time. In prior art 3, a semiconductor memory apparatus is provided with a burn-in test mode detection circuit that may detect a burn-in mode. A switching circuit is provided that may allow the simultaneous selection of two times as many (or more) memory cells than in a normal mode of operation.
Japanese Patent Laid-Open No. 6-76599 (hereinafter referred to as prior art 4) describes a semiconductor storage device that may reduce the time required to select all word lines and thus reduce burn-in time. In prior art 4, a semiconductor storage device can include a word line selection circuit and a test selection circuit that may receive a test signal. When the test signal is inactive, the test selection circuit may be isolated from the word lines and a normal operation may take place. In a normal operation, one of a number of word lines may be selected according to an address signal. When the test signal is active, the word line selection signal may be isolated from the word lines, and a test line selection circuit can select two or more of the word lines.
Japanese Patent Laid-Open No. 7-244998 (hereinafter referred to as prior art 5) describes a semiconductor memory apparatus that can select all memory cells simultaneously during a burn-in test, and at the same time not disturb the normal operating speed of the semiconductor memory apparatus. Reduction in the time required for burn-in test can result. In prior art 5, a semiconductor memory apparatus may include potential supply circuits that provide a Vdd voltage level and a Vxx voltage level to final stages of a word line decoder. Such final stages can include inverters. A selected final stage can receive a Vdd level, while de-selected stages can receive a Vxx. In a normal mode of operation the Vxx level may be set to a voltage equal to or greater than a low supply level Vss. In a burn-in test, the voltage Vxx may be set to the Vdd. In this way, all final word line stages can receive a high voltage level in a burn-in test.
The various described prior art devices 1-5 all address a semiconductor storage device having a number of memory sections of the same type. Such approaches are different than those that include memory sections of different types, as will be described in the embodiments below.
It is also noted that prior art 1 has an uncontrolled output section. A drawback to such an arrangement is that when output data from different memory sections are supplied to the output section simultaneously, a large amount of current can be drawn.
It is further noted that prior art 2 is related to a burn-in test apparatus as opposed to a semiconductor storage device.
It would be desirable to arrive at some way of providing a semiconductor storage device that can have a faster burn-in test time, and yet not suffer from drawbacks during a normal operation, as is the case of other conventional approaches.